The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods for forming a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor.
Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow in a channel formed between the source and drain. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in the channel between the source and drain to produce a device output current. The channel of a planar field-effect transistor is located beneath the top surface of a substrate on which the gate electrode is supported.
Planar field-effect transistors and fin-type field-effect transistors constitute a general category of field-effect transistor structures in which the direction of gated current in the channel is in a horizontal direction that is parallel to the substrate surface. A vertical-transport field-effect transistor is a type of non-planar field-effect transistor in which the source and the drain are arranged at the top and bottom of a semiconductor fin. The direction of gated current in the channel of a vertical-transport field-effect transistor is in a vertical direction relative to the substrate surface and, therefore, in a direction parallel to the height of a semiconductor fin.